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#Fpga projects altera cyclone ii serial
#Fpga projects altera cyclone ii software

GPIO: Seven-segment display, pushbuttons, switches and LEDĪlarm clock SW application. Two things are achieved with this approach compared to Project 3 version: Improved Alarm clock SW application with the use of HAL for timer and UART peripherals and IRQ for timer and push buttons PIO.

ACC_RESULT : Accelerator output value įinished Project 4 & 5: Alarm clock with HAL & IRQ.

1 - Calculation finished (pulse duration: one clock cycle).

DONE_TICK : Current calculation finished pulse.

1 - Start new calculation (valid only if READY = 1).

Interaction between accelerator and Nios II core is achieved via GPIO memory mapped registers as follows: Pseudocode for implemented sqrt function:ĪSMD for the accelerator architecture: Diagram Hardware accelerator for the calculation of y = (nearest whole number that is a square root of x), with x being 32-bit wide and y 16-bit wide (y is padded to 32-bits in order to fit in one Nios II register during system integration). GPIO: communication with the off-chip memory modulesįinished Project 6: Square root hardware accelerator

#Fpga projects altera cyclone ii software

Software test function checks both SRAM and SDRAM modules. Errors are injected on purpose in the last four memory locations. Software is used as a testing platform to confirm memories read and write. This is achieved with a phase shift of -3ns/-54deg for SDRAM module.

SDRAM: ICSI IS42S16400, 4Mx16, as IP Core/Qsys SDRAM controllerĪltera PLL is utilized in order to synchronize off-chip SDRAM timings with the main system.

SRAM: ISSI IS61LV25616AL, 256Kx16, as Avalon MM Slave/SoPC component.

System integration of two RAM chips on the Altera DE2 development board. Ongoing Project 7: Altera DE2 onboard RAM integration

* Note: Two 1-bit registers do not hold an actual value but are used just to trigger a specific command or get statusĪverage number of clock cycles needed for encoding 10 000 samples of data, with both Nios 2 CPU and the accelerator driven from the same 50MHz PLL:

STATUS represent the number of clock cycles it took for accelerator to produce the final value on the output.

STATUS stores the current status of the accelerator:.

11: STATUS - Accelerator status and clock count.

10: FW RESET - Accelerator reset signal.

1 - Load value and start new calculation, valid only if (READY = 1).

01: WE/START - Accelerator write enable and start signal.if (READY = 1), data in the register is the last calculated value.32-bit unsigned integer, current data value in the accelerator.Interaction between accelerator and Nios II core is achieved via memory mapped registers as follows: Additionally, both hardware and software solutions have execution timers which are used to measure performance difference between the two implementations. Software is used as a testing platform to confirm values produced by the hardware accelerator - same encoding scheme is implemented as a C function. Accelerator is implemented as an IP Core/Qsys component in the Nios II system. Simple 6-bit counter is used as a control parameter together with FSM.

#Fpga projects altera cyclone ii serial

Interaction between is achieved through one 32-bit shift register with parallel write from CPU and serial read and write from the accelerator.

Hardware design of a 32-bit convolutional encoder. Ongoing, projects are uploaded as they are being developed csv that are used in a particular design. sopcinfo file available and pin assignments. Every project is a two-part design: hardware description of CPU core with peripherals and accelerators, and C application.

The development board used for the project is Altera DE2 with Cyclone II FPGA and Nios II softcore. Projects cover a range of applications for System on Programmable Chip. Homework assignments as a part of Embedded systems design course VHDL hardware accelerators design on Cyclone II FPGA with microcontroller applications written in C for Nios II core